A DIMM to run your Sims at a whim
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Sooo, you can get more RAM on a single DIMM than I have in most of my servers... combined.
http://www.theregister.co.uk/2015/11/26/time_for_a_new_ram_cram_plan_as_128gb_ddr4_dimms_land/Samsung's started volume production of 128GB DDR4 RDIMMS.
You read that right – a single registered dual inline memory module packing 36 individual 4GB chunks of 3D TSV DDR4 DRAM, for a total of 128GB, can now be yours.
The Register is aware of servers with 96 DIMM slots, which means … WOAH! … 12.2 terabytes of RAM in a single server if you buy Samsung's new babies.
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https://youtu.be/qpMvS1Q1sos
"I got me 100GB of RAM"... Almost there for desktops
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what are the requirements on the server hardware side to support those?
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@Dashrender said:
what are the requirements on the server hardware side to support those?
Same as with any DIMMs... they have to support the size. You'd have to see if the mobo is designed for 128GB or bigger. So far, most are not.
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Most of our server support 1.5TB -2TB of RAM. We have 512GB in most of them.
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@Jason It's less about that and more about will the server support a single 128 GB RAM stick?
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I wonder if there is any type of architectural bottleneck with that much RAM without any additional connection pins?
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@Dashrender said:
@Jason It's less about that and more about will the server support a single 128 GB RAM stick?
Most newer DDR4 controllers on Xeons don't have any per DIMM limitations. Lower end servers might impose some in their motherboard designs though.
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@Dashrender said:
I wonder if there is any type of architectural bottleneck with that much RAM without any additional connection pins?
There is indeed, but it's not the pins that connect to the mobo but all the itty bitty traces from the BGA RAM chips through to the pins. Current RAM is made with something crazy like 10 or 20 layer PCB's (can't recall exact number)
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@Dashrender This is only moderate density DDR3, no where near 128GB. Every color is another layer of copper. Check out his grid size for scale! 4 thousandths of an inch!
Now consider that each trace from the chip to the pin needs to be the same length or you start to induce latency errors. That should blow your mind sufficiently
